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An encore for Magic-1?

Shortly after I declared Magic-1 "hardware complete", I casually mentioned to my wife that I was starting to think about Magic-2.  Her response was swift, and final:

"No, there will be no Magic-2!"

I can't blame her.  She was an extraordinary good sport during Magic-1's design and construction - especially during the wire-wrapping phase.  For most of a year, she put up with electronic junk littering the kitchen table, wire-wrap insulation fragments on the floor and a husband often lost in concentration while the kids were hollering for attention.

She's the love of my life, the woman I plan on growing old with, mother of my children, my partner and best friend.  I have to respect her wishes on this.

 So, there will be no Magic-2.

Instead, we'll call the follow-on project "Magic-16".


The Magic-1 project has been a great success - It's been a fantastic learning experience.  I started off with a set of goals and constraints, and the end result has greatly exceeded my expectations.  However, some of those project goals and constraints required me to make trade-offs that I'd like to address.  In particular, two of my key constraints for Magic-1 were high code density in my ISA design, and limiting the complexity to make it feasible to build the project using wire-wrap and TTL.

The code density requirement led me to create an instruction set architecture  that was powerful and expressive - it packs lots of capability into a small amount of code.  I believe that for compiled C, my Magic architecture beats x86 in code density by 5-10%.  The cost of that, however, was loss of orthagonality and elegance.

Much of the reason I wanted to do Magic-1 was to learn more about electronics and hardware.  However, the construction aspect of Magic-1 forced me to avoid exploring some hardware tricks that would have been fun to try.  For example, pipelining instruction execution would be interesting, but was impractical for Magic-1.  Also, my sense of nostalgia led me to use TTL, but FPGAs are very interesting to me.

So, before I move on to a totally new hobby space, I think I'd like to do another CPU project to address some of these issues.  Here is my first cut at project goals and constraints:

bulletFPGA.  The system will be built using programmable logic.  Specifically, I'll be using an Opal-Kelly XEM3001 development board as a starting point.  Further, I will be expressing the design using Verilog HDL and instantiating it with the Xilinx Web-Pack targeting the XEM3001's 400K gate Spartan III FPGA.
bulletRISC.  The basic design will be a 16-bit Reduced Instruction Set Computer.  However, I intend this CPU to be fully functional and capable of running a multi-tasking real-time operating system.  This implies a C compiler retargeting, user/supervisor modes, traps, interrupts and memory management.
bulletWhole system.  There are lots of FPGA CPU designs around.  However, one thing that I haven't seen a lot of is a simple project that covers the whole system from CPU through compilers, operating system, middleware stack and application programs.  One of the best parts of the Magic-1 project was that it covered that entire space and really let me experience first-hand the interplay between different parts of the system.  So, at the end of the day, I expect the Magic-16 project to yield a complete stand-alone computer running a multi-tasking OS and at the very least serving web pages and allowing interactive command shells.  Oh, and of course it's got to have lots of blinky lights.
bulletRepeatable.  I've had lots of email from people who would like to do a project like Magic-1.  Some have even expressed a desire to build an exact copy of Magic-1.  Though that would be possible, it would be very difficult and potentially very expensive.  I was lucky to get a lot of Magic-1s parts cheaply as surplus, and the custom-made enclosure that Alistair Roe made for Magic-1 would be horribly expensive to duplicate.  One of my goals for this project is that others could take the basic Magic-16 design and fairly cheaply and quickly replicate it.  Not only replicate it, but customize it - add new instructions, tweak the compiler, etc.
bulletShort-time.  I spent four years actively working on Magic-1.  I'm not interested in spending another four years on Magic-16.  I see this project as being completed in months rather than years.  And, my further goal is that once I have it done, someone else could follow along and redo it over a weekend or two.
bulletThe starting specs.  So, here's a rough recap of what I'm shooting for:
bulletCPU & most support functions in FPGA
bulletClean 16-bit pipelined RISC
bulletTrap & interrupt support
bulletUser & supervisor mode support
bulletLCC C compiler retargeting
bulletReal-time OS (probably MicroC-OSII at first)
bulletTCP/IP stack (probably uIP)
bulletNative Ethernet interface
bulletSmall enclosure with lots of LEDs on front panel
bullet$300-$400 budget
bulletEasily customizable
bulletOnce complete, repeatable over a couple of weekends

My current thoughts on Magic-16's instruction set architecture are here.